In U.S. Pat. No. 4,845,677 which issued on July 4, 1989 to Chappell et al., entitled "Pipelined Memory Chip Structure Having Improved Cycle Time", a semiconductor random access memory chip is described wherein the cycle time is less than the access time for any combination of read or write sequence. The memory chip operates in a pipeline manner with more than one access propagating through the chip at any given time and wherein the cycle time is limited by subarray cycles.
U.S. Pat. No. 4,791,324 which issued Dec. 13, 1988 to Hodapp is entitled "CMOS Differential-Amplifier Sense Amplifier" and describes a CMOS sense amplifier for use in a memory that includes two CMOS differential amplifiers. Each differential amplifier receives the same two signals generated from a selected bit line pair and each provides a different one of a complementary pair of signals. U.S. Pat. No. 4,724,344 which issued on Feb. 9, 1988 to Watanabe is entitled "Sensing Amplifier Including Symmetrical And Asymmetrical Load Circuits" and describes a sense amplifier for a random access memory having a first differential amplifying circuit formed of a first pair of transistors having their sources connected together, their gates supplied with differential input signals, and their drains connected with symmetrical type active loads. The second differential amplifying circuit is of a current mirror type formed of a pair of transistors which is connected in series with the first differential amplifying circuit.
In U.S. Pat. No. 4,716,320 which issued on Dec. 29, 1987 to McAdams, entitled "CMOS Sense Amplifier With Isolated Sensing Nodes", a CMOS sense amplifier is described which has the capacitance of the bit lines isolated from the sensing nodes, which allows the sensed differential voltage to be amplified faster than in current CMOS sense amplifiers, since the sensing nodes have significantly lower capacitance than the bit lines.
U.S. Pat. No. 4,694,205 issued on Sept. 15, 1987 to Shu et al. is entitled "Midpoint Sense Amplification Scheme For A CMOS DRAM" and discloses a CMOS, midpoint sense amplification system for controlling the dynamics of the sense amplification phase of the sense cycle of a CMOS DRAM. The system includes a tracking circuit for initiating the first stage of the sense amplification phase when the differential voltage signal attains a first predetermined value.
In U.S. Pat. No. 4,654,831 which issued on Mar. 31, 1987 to Venkatesh, entitled "High Speed CMOS Current Sense Amplifier", a CMOS current sense amplifier circuit is described for providing a high speed of operation that includes a sense amplifier, a dummy sense amplifier and an operational sense amplifier.
In U.S. Pat. No. 4,645,954 issued Feb. 24, 1987 to Schuster entitled "ECL to FET Interface Circuit For Field Effect Transistor Arrays", an interface circuit is described for coupling bipolar ECL logic circuit signals to an FET logic array. The interface receives chip select signals and their complement on a dual rail input line. A small signal amplifier comprising a FET amplifier having an input FET transistor connected through its source and gate to the dual rail input terminals, converts the chip enable signal to a high level clocking signal. An FET dynamic sense amplifier receives a bipolar ECL logic level to be converted to an FET logic level, and receives a reference level from the bipolar transistor logic circuit. Upon clocking of the dynamic sense amplifier by the small signal amplifier, the true and complementary FET logic levels corresponding to the input bipolar logic levels are provided by the dynamic sense amplifier.
U.S. Pat. No. 4,627,033 which issued on Dec. 2, 1986 to Hyslop et al. is entitled "Sense Amplifier With Reduced Instantaneous Power" and describes a CMOS sense amplifier circuit for a dynamic read/write memory that employs cross-coupled n-channel transistors and cross-coupled p-channel transistors returned to the voltage supply and ground through two separate sets of p and n channel transistors selectively activated by sense clocks.
In U.S. Pat. No. 4,604,533 which issued on Aug. 5, 1986 to Miyamoto et al., entitled "Sense Amplifier," a sense amplifier is described including a first differential amplifier and a second differential amplifier. The first differential amplifier has a pair of bipolar transistors as differential input elements which respectively receive differential input signals from a MOS circuit. The second differential amplifier has a pair of MOS transistors as differential input elements which respectively receive differential output signals generated from the first differential amplifier.
In U.S. Pat. No. 4,479,202 which issued on Oct. 23, 1984 to Uchida, entitled "CMOS Sense Amplifier," a memory circuit is described that comprises a plurality of memory cells and a plurality of sense circuits each including first and second input MOS transistors and first and second load MOS transistors of a first channel type and a load circuit connected to the sense circuit and including first to fourth load MOS transistors of a second channel type. The first and second input MOS transistors have their sources connected to each other and their gates connected to receive a differential input signal there between from said memory circuits of the first and second switching transistors which have their sources connected respectively to the drains of said first and second input transistors and their gates connected to a column selection signal.
In the IBM Technical Disclosure Bulletin, Volume 31, No. 7, December 1988 at page 280, a publication entitled "CMOS Preamplified/Clocked Amplifier For ECL Conversion" discloses a CMOS preamplifier/clocked used in the conversion of ECL signal to the large signals used for CMOS devices. A CMOS preamplifier/clocked amplifier receiver which converts small interface signals, such as found in systems using emitter coupled logic (ECL), to the large signals used for complementary metal-oxide-semiconductor (CMOS) devices with high speed and with good tolerances to parametric variations is shown in FIG. 2 of the publication.
In the IBM Technical Disclosure Bullentin, Vol. 31, No. 7, December 1988 at page 409, a publication entitled "High Density Memory Cell Structure with Two Access Transistors" a technique is described whereby a high density dynamic random-access memory cell structure incorporates a pair of access transistors and a capacitor, thereby reducing the structural size of memory cells and improving the immunity to noise.
In a paper by Towler et al. entitled "A128K 6.5 ns Access/5ns Cycle CMOS ECL Static RAM" found in 1989 IEEE ISSCC Digest of Technical Papers, p. 30-31; February, 1989, a pipelined chain of self-resetting circuit macros, initiated by a single clock is shown in FIG. 2. Each block generates its own local reset, allowing the address amplifiers to reset while the decoders are resolving, and the decoders to reset while the subarray is selected and output data is latched. The y-address buffer circuit shown in FIG. 3 of the publication illustrates ECL to CMOS conversion and fast drive development combined with the fast cycle capability which is necessary for pipeline operation. A NOR circuit coupled to output of the buffer circuit initiates fast resetting of the critical path in the buffer circuit.